Within a modern Integrated Circuit (IC) such as a System-on-Chip (SoC), there may be a number of different logic domains. For example, in some architectures, a core circuit (e.g., a Central Processing Unit or CPU) may be located in a first logic domain (e.g., ˜1.1 V) and other circuitry, such as an Input/Output (I/O) interface circuit, may be located in a second logic domain(s) (e.g., ˜1.8 V, 3.3 V, or 5 V). To facilitate the communication of electrical signals between these different domains, level shifters may be used.
As the inventor hereof has recognized, however, level shifters do not work properly if power is not fully present in the logic domain that originates the signal to be communicated. To address these, and other problems, the inventor hereof has developed safe state circuits configured to perform logic domain power-on detection, and to gate a level shifter's output while power is not being properly supplied to a logic domain.